"Jayant R. Sonar" <Jayant.Sonar@xxxxxxxxxxxxxxx> writes:
> I looked into the RTL dumps and found the original call sequence, where
> (r1,r0) is loaded with appropriate address value before adding 3, is valid
> up to IRA phase. The reload phase is optimizing out the important load
> instruction (movsi_long).
>
> Dump before 'postreload' i.e. at 'ira':
> ===========================================================================
> (insn 1613 2944 2945 65 Convert.c:707
> (set (mem/f/i:SI (pre_dec:SI (reg/f:SI 15 sp)) [0 S4 A32])
> (reg:SI 1 r1)) 61 {pushsi_internal} (nil))
>
> (insn 2945 1613 1614 65 Convert.c:707
> (set (reg/f:SI 0 r0 [1056])
> (reg/f:SI 12 r12 [orig:525 D.18812 ] [525])) 67 {*movsi_long} (nil))
>
> (insn 1614 2945 1615 65 Convert.c:707
> (set (reg/f:SI 0 r0 [1056])
> (plus:SI (reg/f:SI 0 r0 [1056])
> (const_int 3 [0x3]))) 1 {addsi3} (nil))
>
>
> Dump of 'postreload':
> ===========================================================================
> (insn 1613 2944 1614 65 Convert.c:707
> (set (mem/f/i:SI (pre_dec:SI (reg/f:SI 15 sp)) [0 S4 A32])
> (reg:SI 1 r1)) 61 {pushsi_internal} (nil))
>
> (insn 1614 1613 1615 65 Convert.c:707
> (set (reg/f:SI 0 r0 [1056])
> (plus:SI (reg/f:SI 0 r0 [1056])
> (const_int 3 [0x3]))) 1 {addsi3} (nil))
>
>
> The instruction 2945 is deleted during reload phase.
Looking at the extra RTL you attached, I see this in the ira dump:
(insn 1605 1604 1607 65 RcHeap.h:351 (set (reg/f:SI 12 r12 [orig:525 D.18812 ] [525])
(reg:SI 0 r0)) 67 {*movsi_long} (nil))
Between this RTL insn and insn 2945, there are no labels, and there is
no modification of either r0 or r12. Therefore, the value in r12 is the
same as the value in r0. Therefore, insn 2945, which sets r0 to r12,
appears unnecessary.
> Just for the reference, giving here again the inappropriate assembly code
> generated:
>
> addd (sp), (r2,r1)
> push $2,r1 <<<<<<<<<<<<<<<<<==================================
> .LCFI548: Insn loading addr in (r1,r0) should be here
> addd $3, (r1,r0) <<<<<<<<<<<<<<<<<<<<==========================
Looking at this, it looks like the addition modifies both r1 and r0.
This implies that your registers hold HImode values, so the modification
to r1 changes the SImode in r0.
If that is why your instruction sequence is wrong, then are you certain
that the value of HARD_REGNO_NREGS is correct?
Ian
