On 10/7/11 9:09 PM, Ian Lance Taylor wrote:
I don't see how this can work reliably in gcc when optimizing. gcc freely rearranges blocks, and there is no way to prevent that. If there are any blocks between "trace" and "post", they may get moved out of the subsection. It's even possible that other
blocks will get moved into the subsection. Ian
OK. I misunderstood what volatile asm ("" : : : "memory") does -- it is not a general code motion barrier, just a motion barrier to compiler-issued reads and writes.
I changed my approach to something like this:
int tmp;
asm volatile ("li %0,0" : "=r"(tmp)); // MIPS load immediate
if (__builtin_expect(!!tmp, 0)) {
C trace code here...
}
By changing the load instruction I can enable and disable the trace code at runtime. It may not be as efficient as the previous approach because of the conditional branch but has the advantage of being very straightforward to understand.
Thanks for the help.
Joe Buehler
