"Dmitry" <mittie@xxxxxxx> writes: > First. How can I set a CC reg in a single CC mode with zero sign and overflow bits? > Zero and sign could be set with the pattern like this: > (set (reg:CCNZ ST0_REGNO)(compare:CCNZ (match_operand:HI 0 "register_operand" "") (const_int 0))) > But the overflow bit I think could be computed like (for HImode): > (set (reg:CCNZV ST0_REGNO)(compare:CCNZV (match_operand:HI 0 "register_operand" "") (const_int 65535))) > But how this two patterns could be merged in one, to set a CC reg in a single CC mode? That would require a peephole of some sort, I suppose. > And the second question. You said "try to clean up unnecessary test instructions afterward". How could I do so? Maybe with peephole optimizations? I mean do I need to search in peepholes for move-test-branch sequences, and if those moves involves accumulators as destinations, and tests operate with those accumulators, I should remove those tests? Yes. Or you might have to do in the machine_reorg pass. Ian
