Greetings Richard,
I wrote a test file as you suggested and included the resulting ASM
code below. I eventually proved myself wrong about the pre-processor
using the address value for the variable in the macro. Although "test0"
below is completed with just the two load and store instructions I guess
the address of the variable is being loaded at run time, after being
assigned by the linker as you said.
It would seem there is little to be gained by adopting the Cortex M3
RAM bitBand memory map for single bit semaphores when using the GCC
compiler. It generates roughly the same number of assembler steps as
using the traditional AND/OR selection of the flag bits within the
containing word. From a cursory look it appears ARM's own compiler may
have special capability for efficiently harnessing the bitBand RAM
memory map.
This issue is of little significance as modern day processors
usually have sufficient RAM capacity that facilitates the use of byte
size variables for single bit flags. Seems like a waste of memory space
but it simply doesn't matter if it is unused space. Should you want
source files for my tests I will send them to you.
Best Regards,
Tom Alldread
/* Includes ------------------------------------------------------------------*/
#include "stm32f10x.h"
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32_RAM_BIT_BAND_H
#define __STM32_RAM_BIT_BAND_H
#ifndef SRAM_BASE
#define SRAM_BASE 0x20000000
#endif
#ifndef SRAM_BB_BASE
#define SRAM_BB_BASE 0x22000000
#endif
/* Includes ------------------------------------------------------------------*/
/* Global variables and constants --------------------------------------------*/
volatile uint32_t tick_500mS_Flags;
#define HEARTBEAT_500MS_FLG (1<<1)
#define RAMBBTEST_0 (uint32_t)&tick_500mS_Flags
#define RAMBBTEST_1 uint32_t)&tick_500mS_Flags-SRAM_BASE)*32 + 1*4+SRAM_BB_BASE
#define RAMBBTEST_2(varName,bit) ((uint32_t)&varName-SRAM_BASE)*32+4*bit+SRAM_BB_BASE
#define RAMBBTEST_3(varName,bit
(*((volatile unsigned int *) (((uint32_t)&varName-SRAM_BASE)
*32+4*bit+SRAM_BB_BASE)))
#define HEARTBEAT_500MS_BBFLG RAMBBTEST_2(tick_500mS_Flags,1)
#define HEARTBEAT_500MS_BBFLG_P RAMBBTEST_3(tick_500mS_Flags,1)
#endif /*__STM32_RAM_BIT_BAND_H*/
/*******************************************************************************
* Function Name : main.
* Description : Main routine.
* Input : None.
* Output : None.
* Return : None.
*******************************************************************************/
int main(void)
{
B480 push {r7}
B085 sub sp, #0x014
AF00 add r7, sp, #0x000
while (1)
{
uint32_t test0, test1, test2, test3, test4;
(*((volatile unsigned int *)0x22005304)) = (uint16_t)1;;
4A16 ldr r2, [pc, #0x058]
F04F0301 mov.w r3, #0x00000001
6013 str r3, [r2, #0x00]
test0 = RAMBBTEST_0;
4B15 ldr r3, [pc, #0x054]
603B str r3, [r7, #0x00]
test1 = RAMBBTEST_1;
4B14 ldr r3, [pc, #0x050]
EA4F1343 mov.w r3, r3, lsl #0x05
F1035308 add.w r3, r3, #0x22000000
F1030304 add.w r3, r3, #0x00000004
607B str r3, [r7, #0x04]
test2 = HEARTBEAT_500MS_BBFLG;
4B10 ldr r3, [pc, #0x040]
EA4F1343 mov.w r3, r3, lsl #0x05
F1035308 add.w r3, r3, #0x22000000
F1030304 add.w r3, r3, #0x00000004
60BB str r3, [r7, #0x08]
test3 = HEARTBEAT_500MS_BBFLG_P = 1;
4B0C ldr r3, [pc, #0x030]
EA4F1343 mov.w r3, r3, lsl #0x05
F1035308 add.w r3, r3, #0x22000000
F1030304 add.w r3, r3, #0x00000004
461A mov r2, r3
F04F0301 mov.w r3, #0x00000001
6013 str r3, [r2, #0x00]
F04F0301 mov.w r3, #0x00000001
60FB str r3, [r7, #0x0C]
test4 = (uint32_t)&HEARTBEAT_500MS_BBFLG_P;
4B05 ldr r3, [pc, #0x014]
EA4F1343 mov.w r3, r3, lsl #0x05
F1035308 add.w r3, r3, #0x22000000
F1030304 add.w r3, r3, #0x00000004
613B str r3, [r7, #0x10]
}
E7D2 b 0x0800032A
5304 strh r4, [r0, r4]
2200 movs r2, #0x00
003C lsls r4, r7, #0x00
2000 movs r0, #0x00
0000 lsls r0, r0, #0x00
}
