On Mon, 2009-08-17 at 17:18 -0700, Ted Krovetz wrote:
> Hello,
>
> I'm writing a small low-level routine using inline ARM assembly. The
> following gives me trouble:
>
> #include <stdint.h>
> uint64_t foo(uint64_t a)
> {
> asm ("adds %0,%0,%0\n\t"
> "adcs %H0,%H0,%H0\n\t"
> "eorc %0,#0x51\n\t"
> "eorcs %H0,#0x80000000"
> : "+r"(a) : : "cc");
> return a;
> }
>
> thecus> gcc-4.4 test.c -march=armv5te -O2 -c
> /tmp/cc1CraGk.s: Assembler messages:
> /tmp/cc1CraGk.s:28: Error: bad instruction `eorc r3,#0x51'
>
> If I use eorcs or eor instead of eorc then there is no complier
> complaint, but I need both eor's to be conditional on the same carry
> flag (from adcs) so cannot use 's' in the first eor case.
>
> Why won't gcc (or is it gas) let me use eorc? It is a legitimate
> opcode for ARM, as far as I can tell.
>
No it isn't.
the instruction is eor<cond> where cond is one of eq ne gt lt le ge cc
cs hi lo vs vc pl mi (and al - but that's the same as not putting a
condition at all).
the executed operation is
if (<cond> is true) then eor ...
R.
