Re: AMD dual core opetron optimization

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* kernel coder:

> Main idea of this project is to read packets from gigabit ethernet
> card and get the required information from packets in less than 200
> cycles.The algorithem is so efficient that it will take less than 200
> cycles if ideal envoirnment is provided.Ideal envoirnment also means
> that once data is brought into cache ,then it remains into cache till
> packet processing is complete.

Write the thing in machine code.  If it has to fit in 200 cycles, the
code will be so small that maintenance is not an issue.

Your NIC likely performs interrupt coalescing, so you might be able to
process multiple packets in parallel, increasing utilization of
execution units.

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