Bharati Bhole writes:
> On 11/2/06, Daniel Berlin <dberlin@xxxxxxxxxxx> wrote:
> > > I want to know what part of rtx each field in this structure stores.
> > > While tracing through gdb i tried to print the rtx, and i was not able
> > > to understand that. Could u please explain me it with a sample RTX
> > > that what value these fields have.
> > >
> >
> > The macros used to access the rtl fields in rtl.h explain what part of
> > each field they access and what they treat that object as.
> >
> > The definitions of rtl in rtl.def define what each portion of a piece
> > of valid RTL is structured as.
> > > Bharati.
> > >
> >
>
> I have gone through the structure but i still dont get it.
> Could anybody please tell me, if the following insn is a sample insn,
> how will the rtx structure look like -
> (define_insn "subsi3_carry_zext"
> [(set (match_operand:DI 0 "register_operand" "=rm,r")
> (zero_extend:DI
> (minus:SI (match_operand:SI 1 "register_operand" "0,0")
> (plus:SI (match_operand:SI 3
> "ix86_carry_flag_operator" "")
> (match_operand:SI 2 "general_operand" "ri,rm")))))
> (clobber (reg:CC FLAGS_REG))]
> "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
> "sbb{l}\t{%2, %k0|%k0, %2}"
> [(set_attr "type" "alu")
> (set_attr "pent_pair" "pu")
> (set_attr "mode" "SI")])
But this isn't a simple insn, it's a machine description pattern.
These are described in Section 13, Machine Descriptions.
Andrew.
