Please do not reply directly to this email. All additional comments should be made in the comments box of this bug. Summary: Review Request: verilator - A fast simulator for synthesizable verilog HDL https://bugzilla.redhat.com/show_bug.cgi?id=468515 Summary: Review Request: verilator - A fast simulator for synthesizable verilog HDL Product: Fedora Version: rawhide Platform: All OS/Version: Linux Status: NEW Severity: medium Priority: medium Component: Package Review AssignedTo: nobody@xxxxxxxxxxxxxxxxx ReportedBy: lbrooks@xxxxxxx QAContact: extras-qa@xxxxxxxxxxxxxxxxx CC: notting@xxxxxxxxxx, fedora-package-review@xxxxxxxxxx Estimated Hours: 0.0 Classification: Fedora Spec URL: http://brooks.nu/~lane/verilator.spec SRPM URL: http://brooks.nu/~lane/verilator-3.680-2.fc10.src.rpm Description: Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams. Because of systemc licensing issues, the verilator dependancies on systemc are not included with this package. This means the perl-verilog, perl-systemc, and systemc functionality that is integrated into verilator will only work if those packages are installed separately. This package, therefore, supports the verilog features of verilator (including vcd generation via the --trace option). -- Configure bugmail: https://bugzilla.redhat.com/userprefs.cgi?tab=email ------- You are receiving this mail because: ------- You are on the CC list for the bug. _______________________________________________ Fedora-package-review mailing list Fedora-package-review@xxxxxxxxxx http://www.redhat.com/mailman/listinfo/fedora-package-review