[Bug 1988151] Review Request: atomic-queue - C++ lockless queue

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https://bugzilla.redhat.com/show_bug.cgi?id=1988151



--- Comment #7 from Ben Beasley <code@xxxxxxxxxxxxxxxxxx> ---
I’ll go ahead and create the tracker bugs for the missing architectures. It
might still be possible to resolve them with some care, and perhaps
consultation with upstream.

I think I now basically understand the requirements for a minimal “empty”
spin_loop_pause(). The fallback for ARMs that don’t support the “yield”
instruction is a good example. It’s a “nop” instruction plus a memory clobber,
to create a “compiler barrier” that keeps the compiler from eliding, hoisting,
or otherwise subverting the pause function. This is exactly what the example
you gave for PowerPC is doing. “or 1 1 1” is an idiomatic nop for PowerPC,
or’ing a register with itself to waste time with no effect.

I’m not so sure about the s390x example from Linux. As far as I can understand
from the limited documentation I’ve found, it’s a conditional branch where the
condition is zero so the branch is not taken. However, it seems the first
argument somehow causes the BCR instruction to have a synchronization function
as well (https://github.com/golang/go/issues/42479), although I haven’t found
good documentation on the exact effects. I assume this is intentional, and I
wonder why it is needed.


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