Re: Fedora 32 Self-Contained Change proposal: Additional buildroot to test x86-64 micro-architecture update

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I have some concerns about this proposal. Given that this change was essentially unanimously rejected, this line stood out to me:

> * As soon as feature is accepted by the community, there will be a
> smooth process to update baseline in the main Fedora, as all packages
> will be already verified and tested to work against it.

This makes it sound as if this change is inevitable and that the community is simply being stubborn or ignorant of its importance. The current (and foreseeable) situation is that Intel will continue to use SIMD extensions as a way to help segment its processor lines, for example we know that the new low power microarchitecture, Tremont, will not have AVX2 support [1].

Currently, Intel's atom [2], celeron [3], and pentium [4] processors do not have AVX2 support. Not to mention that this change would eliminate support for all AMD processors made before 2017 (pre-Zen) and all Intel processors made before 2013 (pre-Haswell) so I am worried that this is a step towards abandoning a large swath of processors for reasons and goals that have not been fully articulated.

So here are some questions that would help me better understand this proposal:

1. The motivation behind the change is clearly performance, but what packages and/or use cases are expected to see a significant increase in performance? What testing/benchmarking has been done to demonstrate these improvements, and where can we see the results?

2. Since it is likely that new SIMD extensions will be implemented in the future, what are the factors considered for moving the baseline of Fedora? What is an acceptable age for a processor to be before it is unsupported? Do we want Fedora to only target mid and high end Intel processor SKUs? What performance increases (and for which packages) merit consideration for bumping the baseline?

3. Why was AVX2 chosen as the baseline? Specifically, why was it chosen over a more conservative increase to something like SSE4.1/4.2, or a more aggressive increase to AVX512?

4. Given that the author of the proposal is expecting this change in x86_64 baseline to be implemented at some point in the future, what is the projected timeline and what is currently blocking this change from being proposed again (besides the community)?

[1] https://en.wikichip.org/wiki/intel/microarchitectures/tremont
[2] https://ark.intel.com/content/www/us/en/ark/products/184994/intel-atom-processor-c3336-4m-cache-1-50-ghz.html
[3] https://ark.intel.com/content/www/us/en/ark/products/134879/intel-celeron-processor-g4950-2m-cache-3-30-ghz.html
[4] https://ark.intel.com/content/www/us/en/ark/products/135457/intel-pentium-gold-g5620-processor-4m-cache-4-00-ghz.html
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