Frantisek Kluknavsky wrote:
> People with interest in secondary architectures might oppose that.
Which architectures are the problem? OpenBLAS currently supports:
| 2. Supported Architecture
|
| X86 : Pentium3 Katmai
| Coppermine
| Athlon (not well optimized, though)
| PentiumM Banias, Yonah
| Pentium4 Northwood
| Nocona (Prescott)
| Core 2 Woodcrest
| Core 2 Penryn
| Nehalem-EP Corei{3,5,7}
| Atom
| AMD Opteron
| AMD Barlcelona, Shanghai, Istanbul
| VIA NANO
|
| X86_64: Pentium4 Nocona
| Core 2 Woodcrest
| Core 2 Penryn
| Nehalem
| Atom
| AMD Opteron
| AMD Barlcelona, Shanghai, Istanbul
| VIA NANO
|
| IA64 : Itanium2
|
| Alpha : EV4, EV5, EV6
|
| POWER : POWER4
| PPC970/PPC970FX
| PPC970MP
| CELL (PPU only)
| POWER5
| PPC440 (QCDOC)
| PPC440FP2(BG/L)
| POWERPC G4(PPC7450)
| POWER6
|
| SPARC : SPARC IV
| SPARC VI, VII (Fujitsu chip)
|
| MIPS64/32: Sicortex
| Additional support CPU:
| x86/x86-64:
| * Intel Xeon 56xx (Westmere): Used GotoBLAS2 Nehalem codes.
| * Intel Sandy Bridge: Optimized Level-3 BLAS with AVX on x86-64.
| * Intel Haswell: Optimized Level-3 BLAS with AVX on x86-64 (identical to
| Sandy Bridge).
| * AMD Bobcat: Used GotoBLAS2 Barcelona codes.
| * AMD Bulldozer: x86-64 S/DGEMM AVX kernels. (Thank Werner Saar)
| * AMD PILEDRIVER: Used Bulldozer codes.
| MIPS64:
| * ICT Loongson 3A: Optimized Level-3 BLAS and the part of Level-1,2.
| * ICT Loongson 3B: Experimental
(and as I said, ARM is being worked on as we speak, so it's not listed yet,
but will be very soon).
> Perhabs if we ensure binary compatibility then we can make them freely
> interchangeable.
I also like the binary compatibility approach (used for ATLAS in the past:
you build against reference BLAS/LAPACK and then get whatever one you want
pulled in at runtime), but Susi Lehtola wrote that it is not supported (or
for ATLAS, not anymore) by upstream.
Kevin Kofler
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