On Aug 26, 2015 10:46, "Rob Clark" <robdclark@xxxxxxxxx> wrote:
>
> btw, w/ some of these clk rounding issues, I suspect we need 'struct
> drm_display_mode' to be able to represent mode clock with greater
> accuracy than Khz..
Interesting point! However, in this case I had to adjust the clock hundreds of kHz to make it tick over one step of hs_zero, so it might not be absolutely necessary here. Do we need better than 10ppm accuracy for display timing (assuming 100MHz pixel clock, 1kHz step size and that I did the math correctly)? We don't even have kHz accuracy with the PLLs in the QC platforms we currently use..
I think the rounding error happens with the smaller numbers / intermediate results but maybe clock should be represented in Hz internally anyway? Not sure if it's worth changing the external-facing representation though?
/wj
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