Comment # 7
on bug 91509
from Roland Scheidegger
(In reply to Michel Dänzer from comment #6) > FWIW, the (micro-)tile size is always 8x8. With macro-tiling (called 2D > tiling with current GPUs) enabled, the pitch (and height, for calculating > the memory allocation size) must usually be aligned to a macro-tile > boundary. Not sure offhand how to calculate the macro-tile size on those old > GPUs though. I'm not sure if micro/macro-tiling really apply to r200 depth tiled buffers, the pattern is quite different to color tiling. Actually the docs say for rv200: DEPTHOFFSET: "...128 bit aligned address. When tiling the offset must be tile-aligned (2KB)" DEPTHPITCH:"Pitch is specified in multiples of 8 pixels. When tiling the pitch must be tile-aligned" And for R200: DEPTHOFFSET: "Z Buffer Offset must be aligned to 4KB" DEPTHPITCH: "Pitch is specified in multiples of 32 pixels" So, in r200, depthoffset wording takes into account that it is always tiled, however depth pitch doesn't mention it at all, making it sound like no specific alignment due to tiling would be required. Of course I don't know how true that really is, in particular for z16 it seems it cannot be true (because the formula in the driver for tiling only uses (pitch >> 7) both for z16 and z32). Even if those 128bytes there would be sufficient you're probably quite right that we're also missing height alignment adjustment (if we'd use 128 bytes for width and 32 alignment for height that would give us the 4KB aligned blocks overall too). Oh, and based on the doc wording clearly the depth pitch would be wrongly aligned on r100 too (even though based on the formula the driver uses (pitch >> 6) it looks like it could work).
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