On Mon, Feb 16, 2015 at 01:43:07PM +0100, Volker Vogelhuber wrote: > I'm currently trying to setup a rendering pipe on an Intel Baytrail E3845 > cpu. > In our product we want to have an FPGA streaming video images to a > predefined memory area using bus master dma and render those images using > OpenGL. So far this works in a preliminary state. > We now have the security requirement that in case the CPU (software/kernel > driver) crashes for what ever reason, the GPU display signal should still > output at least the video images (obviously any additional render stuff will > not be available anymore). My question is now, would it be possible to get > the physical address of the DRM front buffer, so that I can provide this > address to the FPGA (connected via PCIe) and is it possible to have the GPU > still reading the last front buffer for the display output while the FPGA > writes to that area. So I would think that the GPU has some kind of DMA > engine running, that continuously reading the last front buffer until > switched to another buffer by the CPU. So even if the CPU does not control > the GPU anymore, it might be possible to have the front buffer updated by > the FPGA directly. Of course there will be tearing artefacts as no VSYNC > will be available but that wouldn't be an issue so far. Just share buffers between your fpga driver and the i915 driver using prime/dma-buf and before each pageflip tell your fpga driver to render into the new buffer. We don't have any interfaces to tell userspace physical addresses of anything, and that's fairly intentional - the kernel is and must be in control of memory management. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ dri-devel mailing list dri-devel@xxxxxxxxxxxxxxxxxxxxx http://lists.freedesktop.org/mailman/listinfo/dri-devel
