[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

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Comment # 34 on bug 73378 from
(In reply to Christian König from comment #32)

> Strange, the hardware docs say this is for routing the reset signal and
> shouldn't be touched by the driver, e.g. it should always be 1.

Is this some kind of open hardware docs? Or just internal? Maybe I missed
something


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