[Bug 73378] [drm:radeon_uvd_send_upll_ctlreq] *ERROR* Timeout setting UVD clocks!

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Comment # 28 on bug 73378 from
(In reply to Christian König from comment #27)
> > 
> > [    2.237380] [drm] At call 1
> > [    3.278457] [drm] At call 2
> > [    3.288474] [drm] Passed!
> 
> Well just that I got it right: The first call runs into an error, but after
> issuing the reset and reprogramming everything the second call succeeds?

Yep, the DRM_INFO was at the "break" line in a loop of
radeon_uvd_send_upll_ctlreq.

> 
> In this case I would just speculate that somebody (the BIOS?) programmed the
> PLL with such incorrect values that it locked up and need a reset to work
> properly again.
> 
> Can you just reduce the first call to radeon_uvd_send_upll_ctlreq to a
> warning and continue? If the second call works we have successfully
> programmed the PLL and everything is fine.

But does it differ from previous behaviour when both calls were reduced to
return success even on timeout? Could the first call lock PLL somehow?

I'll try again today.


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