Comment # 27
on bug 73378
from Christian König
(In reply to Chernovsky Oleg from comment #25) > It's the first call to this function in si_set_uvd_clocks that's failing. > Doesn't work in bypass mode? Or maybe too low mdelay before call? > > [ 2.237380] [drm] At call 1 > [ 3.278457] [drm] At call 2 > [ 3.288474] [drm] Passed! Well just that I got it right: The first call runs into an error, but after issuing the reset and reprogramming everything the second call succeeds? In this case I would just speculate that somebody (the BIOS?) programmed the PLL with such incorrect values that it locked up and need a reset to work properly again. Can you just reduce the first call to radeon_uvd_send_upll_ctlreq to a warning and continue? If the second call works we have successfully programmed the PLL and everything is fine.
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