On Mon, Sep 8, 2014 at 9:15 PM, Michel Dänzer <michel@xxxxxxxxxxx> wrote:
> On 09.09.2014 09:47, Michel Dänzer wrote:
>> On 09.09.2014 02:36, Alex Deucher wrote:
>>>
>>> Updated version with comments integrated.
>>
>> [...]
>>
>>> @@ -314,10 +314,12 @@ int radeon_bo_pin_restricted(struct radeon_bo
>>> *bo, u32 domain, u64 max_offset,
>>> unsigned lpfn = 0;
>>>
>>> /* force to pin into visible video ram */
>>> - if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
>>> - lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
>>> - else
>>> + if (bo->placements[i].flags & TTM_PL_FLAG_VRAM) {
>>> + if (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS))
>>> + lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
>>> + } else {
>>> lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
>>> + }
>>
>> The else block can be removed as well, but that can be done in another
>> patch.
>
> Actually, I just noticed a problem, the following if statement:
>
>> if (max_offset)
>> lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
>
> This will ignore max_offset if lpfn is 0. So either go with v1 of this hunk,
> or rebase on top of the patch below.
>
Rebased on your patch and attached.
Alex
>
> From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@xxxxxxx>
> Date: Tue, 9 Sep 2014 10:09:23 +0900
> Subject: [PATCH] drm/radeon: Clean up assignment of TTM placement lpfn member
> for pinning
> MIME-Version: 1.0
> Content-Type: text/plain; charset=UTF-8
> Content-Transfer-Encoding: 8bit
>
> Signed-off-by: Michel Dänzer <michel.daenzer@xxxxxxx>
> ---
> drivers/gpu/drm/radeon/radeon_object.c | 12 ++++--------
> 1 file changed, 4 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
> index 908ea541..8ec8150 100644
> --- a/drivers/gpu/drm/radeon/radeon_object.c
> +++ b/drivers/gpu/drm/radeon/radeon_object.c
> @@ -307,18 +307,14 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
> }
> radeon_ttm_placement_from_domain(bo, domain);
> for (i = 0; i < bo->placement.num_placement; i++) {
> - unsigned lpfn = 0;
> -
> /* force to pin into visible video ram */
> if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
> - lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
> + bo->placements[i].lpfn =
> + min(bo->rdev->mc.visible_vram_size, max_offset)
> + >> PAGE_SHIFT;
> else
> - lpfn = bo->rdev->mc.gtt_size >> PAGE_SHIFT; /* ??? */
> -
> - if (max_offset)
> - lpfn = min (lpfn, (unsigned)(max_offset >> PAGE_SHIFT));
> + bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
>
> - bo->placements[i].lpfn = lpfn;
> bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
> }
>
> --
> 2.1.0
>
>
> --
> Earthling Michel Dänzer | http://www.amd.com
> Libre software enthusiast | Mesa and X developer
From 998fabb91851cef7c70e0f3920e45c70da301647 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Tue, 9 Sep 2014 12:24:33 -0400
Subject: [PATCH] drm/radeon: add RADEON_GEM_NO_CPU_ACCESS BO creation flag
(v3)
Allows pinning of buffers in the non-CPU visible portion of
vram.
v2: incorporate Michel's comments.
v3: rebase on Michel's patch
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
---
drivers/gpu/drm/radeon/radeon_object.c | 3 ++-
include/uapi/drm/radeon_drm.h | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 68ab122..0d54993 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -312,7 +312,8 @@ int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
radeon_ttm_placement_from_domain(bo, domain);
for (i = 0; i < bo->placement.num_placement; i++) {
/* force to pin into visible video ram */
- if (bo->placements[i].flags & TTM_PL_FLAG_VRAM)
+ if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
+ (!(bo->flags & RADEON_GEM_NO_CPU_ACCESS)))
bo->placements[i].lpfn =
min(bo->rdev->mc.visible_vram_size, max_offset)
>> PAGE_SHIFT;
diff --git a/include/uapi/drm/radeon_drm.h b/include/uapi/drm/radeon_drm.h
index f755f20..50d0fb4 100644
--- a/include/uapi/drm/radeon_drm.h
+++ b/include/uapi/drm/radeon_drm.h
@@ -803,6 +803,8 @@ struct drm_radeon_gem_info {
#define RADEON_GEM_GTT_WC (1 << 2)
/* BO is expected to be accessed by the CPU */
#define RADEON_GEM_CPU_ACCESS (1 << 3)
+/* CPU access is not expected to work for this BO */
+#define RADEON_GEM_NO_CPU_ACCESS (1 << 4)
struct drm_radeon_gem_create {
uint64_t size;
--
1.8.3.1
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