Hello Kees,
Thanks for your feedback. Let me first reassure you that this fall-through is indeed intentional: vdiv should be set regardless of the clock source. A comment line would definitely be in place though for future nouveau hackers.
In read_pll, post_div can never be zero in valid execution. If the register-read returns zero, the GPU has either fallen off the bus, or crashed because someone set a divider of 0. I agree that this is not very robust and will probably lead to a divide-by-zero on hardware failure. Checking it doesn't harm I bet!
I will propose a patch addressing these issues as soon as I find some free time. Thanks again for the feedback. Yours,
Roy
--- Ursprüngliche Nachricht ---
Von: Kees Cook <keescook@xxxxxxxxxx>
Datum: 20:51:22 26-12-2013
An: Roy Spliet <rspliet@xxxxxxxxxx>
Betreff: nouveau nvaa clock missing break?
> Hi,
>
> Just curious if this code is missing a "break" or not...
>
> /drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c: 373 in nvaa_clock_prog()
>
>
> switch (priv->vsrc) {
> case nv_clk_src_cclk:
> mast |= 0x00400000;
> default:
> nv_wr32(clk, 0x4600, priv->vdiv);
> }
>
> Coverity noticed it as CID 1135671. If it's intentional, it might be
> nice to add a "fall through" comment there.
>
> Coverity also complained about read_pll (CID 1135670) where post_div
> could (unlikely) be 0 and used for a divide-by-zero.
>
> Thanks!
>
> -Kees
>
> --
> Kees Cook
> Chrome OS Security
>
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