nouveau nvaa clock missing break?

[Kees Cook <keescook@xxxxxxxxxx>]

Hi,

Just curious if this code is missing a "break" or not...

/drivers/gpu/drm/nouveau/core/subdev/clock/nvaa.c: 373 in nvaa_clock_prog()

        switch (priv->vsrc) {
        case nv_clk_src_cclk:
                mast |= 0x00400000;
        default:
                nv_wr32(clk, 0x4600, priv->vdiv);
        }

Coverity noticed it as CID 1135671. If it's intentional, it might be
nice to add a "fall through" comment there.

Coverity also complained about read_pll (CID 1135670) where post_div
could (unlikely) be 0 and used for a divide-by-zero.

Thanks!

-Kees

-- 
Kees Cook
Chrome OS Security
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