On Fri, Feb 21, 2025 at 12:37:40AM +0100, Marijn Suijten wrote: > On 2025-02-20 12:26:24, Dmitry Baryshkov wrote: > > Since DPU 5.0 CTL blocks do not require DPU_CTL_SPLIT_DISPLAY, as single > > CTL is used for both interfaces. As both RM and encoder now handle > > active CTLs, drop that feature bit. > > I was wondering if this bit only existed to ensure the right "pair" of CTLs > exist: not on DPU 4.0, but on DPU 3.0 we see that CTL_0 and CTL_2 have this bit > but not CTL_1. Meaning that split display can only work when that specific pair > of CTL_0 and CTL_2 is used in conjunction? Unfortunately I don't have a deep knowledge of those platforms and I don't have a way to test it. My SDM660 board (IFC6560) doesn't have DSI1 routed anywhere. > > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > > Reviewed-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> > -- With best wishes Dmitry
