Applied. Thanks!
Alex
On Mon, Feb 24, 2025 at 8:43 AM <linux@xxxxxxxxxxx> wrote:
>
> From: "Dr. David Alan Gilbert" <linux@xxxxxxxxxxx>
>
> The last use of optc3_fpu_set_vrr_m_const() was removed in 2022's
> commit 64f991590ff4 ("drm/amd/display: Fix a compilation failure on PowerPC
> caused by FPU code")
> which removed the only caller (with a similar) name.
>
> Remove it.
>
> Signed-off-by: Dr. David Alan Gilbert <linux@xxxxxxxxxxx>
> ---
> .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.c | 76 -------------------
> .../drm/amd/display/dc/dml/dcn30/dcn30_fpu.h | 3 -
> 2 files changed, 79 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
> index aac0a0ae2966..88789987bdbc 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
> @@ -178,82 +178,6 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = {
> };
>
>
> -void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,
> - double vtotal_avg)
> -{
> - struct optc *optc1 = DCN10TG_FROM_TG(optc);
> - double vtotal_min, vtotal_max;
> - double ratio, modulo, phase;
> - uint32_t vblank_start;
> - uint32_t v_total_mask_value = 0;
> -
> - dc_assert_fp_enabled();
> -
> - /* Compute VTOTAL_MIN and VTOTAL_MAX, so that
> - * VOTAL_MAX - VTOTAL_MIN = 1
> - */
> - v_total_mask_value = 16;
> - vtotal_min = dcn_bw_floor(vtotal_avg);
> - vtotal_max = dcn_bw_ceil(vtotal_avg);
> -
> - /* Check that bottom VBLANK is at least 2 lines tall when running with
> - * VTOTAL_MIN. Note that VTOTAL registers are defined as 'total number
> - * of lines in a frame - 1'.
> - */
> - REG_GET(OTG_V_BLANK_START_END, OTG_V_BLANK_START,
> - &vblank_start);
> - ASSERT(vtotal_min >= vblank_start + 1);
> -
> - /* Special case where the average frame rate can be achieved
> - * without using the DTO
> - */
> - if (vtotal_min == vtotal_max) {
> - REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);
> -
> - optc->funcs->set_vtotal_min_max(optc, 0, 0);
> - REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);
> - REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);
> - REG_UPDATE_3(OTG_V_TOTAL_CONTROL,
> - OTG_V_TOTAL_MIN_SEL, 0,
> - OTG_V_TOTAL_MAX_SEL, 0,
> - OTG_SET_V_TOTAL_MIN_MASK_EN, 0);
> - return;
> - }
> -
> - ratio = vtotal_max - vtotal_avg;
> - modulo = 65536.0 * 65536.0 - 1.0; /* 2^32 - 1 */
> - phase = ratio * modulo;
> -
> - /* Special cases where the DTO phase gets rounded to 0 or
> - * to DTO modulo
> - */
> - if (phase <= 0 || phase >= modulo) {
> - REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL,
> - phase <= 0 ?
> - (uint32_t)vtotal_max : (uint32_t)vtotal_min);
> - REG_SET(OTG_V_TOTAL_MIN, 0, OTG_V_TOTAL_MIN, 0);
> - REG_SET(OTG_V_TOTAL_MAX, 0, OTG_V_TOTAL_MAX, 0);
> - REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, 0);
> - REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, 0);
> - REG_UPDATE_3(OTG_V_TOTAL_CONTROL,
> - OTG_V_TOTAL_MIN_SEL, 0,
> - OTG_V_TOTAL_MAX_SEL, 0,
> - OTG_SET_V_TOTAL_MIN_MASK_EN, 0);
> - return;
> - }
> - REG_UPDATE_6(OTG_V_TOTAL_CONTROL,
> - OTG_V_TOTAL_MIN_SEL, 1,
> - OTG_V_TOTAL_MAX_SEL, 1,
> - OTG_SET_V_TOTAL_MIN_MASK_EN, 1,
> - OTG_SET_V_TOTAL_MIN_MASK, v_total_mask_value,
> - OTG_VTOTAL_MID_REPLACING_MIN_EN, 0,
> - OTG_VTOTAL_MID_REPLACING_MAX_EN, 0);
> - REG_SET(OTG_V_TOTAL, 0, OTG_V_TOTAL, (uint32_t)vtotal_min);
> - optc->funcs->set_vtotal_min_max(optc, vtotal_min, vtotal_max);
> - REG_SET(OTG_M_CONST_DTO0, 0, OTG_M_CONST_DTO_PHASE, (uint32_t)phase);
> - REG_SET(OTG_M_CONST_DTO1, 0, OTG_M_CONST_DTO_MODULO, (uint32_t)modulo);
> -}
> -
> void dcn30_fpu_populate_dml_writeback_from_context(
> struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes)
> {
> diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
> index cab864095ce7..e3b6ad6a8784 100644
> --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
> +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.h
> @@ -29,9 +29,6 @@
> #include "core_types.h"
> #include "dcn20/dcn20_optc.h"
>
> -void optc3_fpu_set_vrr_m_const(struct timing_generator *optc,
> - double vtotal_avg);
> -
> void dcn30_fpu_populate_dml_writeback_from_context(
> struct dc *dc, struct resource_context *res_ctx, display_e2e_pipe_params_st *pipes);
>
> --
> 2.48.1
>
