On Fri, Feb 21, 2025 at 04:24:28PM +0100, Krzysztof Kozlowski wrote:
> v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register
> differences and new implementations of setup_alpha_out,
> setup_border_color and so one for this.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>
> ---
>
> Changes in v3:
> 1. New patch, split from previous big DPU v12.0.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 20 +++++---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++++--
> 2 files changed, 94 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index b9fe3a7343d54f6f8b5aad7982928d5fc728bd61..7a35939ece180c15898b2eaa2f1f451767c741ae 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -319,15 +319,21 @@ static bool dpu_crtc_get_scanout_position(struct drm_crtc *crtc,
> return true;
> }
>
> -static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> - struct dpu_plane_state *pstate, const struct msm_format *format)
> +static void _dpu_crtc_setup_blend_cfg(const struct dpu_hw_ctl *ctl,
> + struct dpu_crtc_mixer *mixer,
> + struct dpu_plane_state *pstate,
> + const struct msm_format *format)
> {
> struct dpu_hw_mixer *lm = mixer->hw_lm;
> uint32_t blend_op;
> - uint32_t fg_alpha, bg_alpha;
> + uint32_t fg_alpha, bg_alpha, max_alpha;
>
> fg_alpha = pstate->base.alpha >> 8;
> - bg_alpha = 0xff - fg_alpha;
> + if (ctl->mdss_ver->core_major_ver < 12)
> + max_alpha = 0xff;
> + else
> + max_alpha = 0x3ff;
So, CTL is passed only to get struct dpu_mdss_version? It can either be
passed directly or fetched via dpu_kms->catalog->mdss_ver
> + bg_alpha = max_alpha - fg_alpha;
>
> /* default to opaque blending */
> if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE ||
> @@ -337,7 +343,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> } else if (pstate->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI) {
> blend_op = DPU_BLEND_FG_ALPHA_FG_CONST |
> DPU_BLEND_BG_ALPHA_FG_PIXEL;
> - if (fg_alpha != 0xff) {
> + if (fg_alpha != max_alpha) {
> bg_alpha = fg_alpha;
> blend_op |= DPU_BLEND_BG_MOD_ALPHA |
> DPU_BLEND_BG_INV_MOD_ALPHA;
> @@ -348,7 +354,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer,
> /* coverage blending */
> blend_op = DPU_BLEND_FG_ALPHA_FG_PIXEL |
> DPU_BLEND_BG_ALPHA_FG_PIXEL;
> - if (fg_alpha != 0xff) {
> + if (fg_alpha != max_alpha) {
> bg_alpha = fg_alpha;
> blend_op |= DPU_BLEND_FG_MOD_ALPHA |
> DPU_BLEND_FG_INV_MOD_ALPHA |
> @@ -482,7 +488,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc,
>
> /* blend config update */
> for (lm_idx = 0; lm_idx < cstate->num_mixers; lm_idx++) {
> - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format);
> + _dpu_crtc_setup_blend_cfg(ctl, mixer + lm_idx, pstate, format);
>
> if (bg_alpha_enable && !format->alpha_enable)
> mixer[lm_idx].mixer_op_mode = 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..75bf3521b03c8e243ccfe1fc226aa71f23b296df 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c
> @@ -19,12 +19,20 @@
>
> /* These register are offset to mixer base + stage base */
> #define LM_BLEND0_OP 0x00
> +
> +/* <v12 DPU with offset to mixer base + stage base */
> #define LM_BLEND0_CONST_ALPHA 0x04
> #define LM_FG_COLOR_FILL_COLOR_0 0x08
> #define LM_FG_COLOR_FILL_COLOR_1 0x0C
lowercase hex
> #define LM_FG_COLOR_FILL_SIZE 0x10
> #define LM_FG_COLOR_FILL_XY 0x14
>
> +/* >= v12 DPU */
> +#define LM_BORDER_COLOR_0_V12 0x1C
lowercase hex
> +#define LM_BORDER_COLOR_1_V12 0x20
> +
> +/* >= v12 DPU with offset to mixer base + stage base */
> +#define LM_BLEND0_CONST_ALPHA_V12 0x08
This doesn't seem to be aligned properly
> #define LM_BLEND0_FG_ALPHA 0x04
> #define LM_BLEND0_BG_ALPHA 0x08
>
--
With best wishes
Dmitry
