On Wed, Feb 19, 2025 at 05:23:33PM +0100, Krzysztof Kozlowski wrote: > Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to > avoid hard-coding bit masks and shifts and make the code a bit more > readable. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > > --- > > Changes in v5: > 1. Split part touching pll_7nm_register() to new patch. > 2. Update commit msg. > > Changes in v4: > 1. Add mising bitfield.h include > 2. One more FIELD_GET and DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL (Dmitry) > > Changes in v3: > 1. Use FIELD_GET > 2. Keep separate bit_clk_div and pix_clk_div > 3. Rebase (some things moved to previous patches) > > Changes in v2: > 1. New patch > --- > drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 10 ++++++---- > 1 file changed, 6 insertions(+), 4 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> -- With best wishes Dmitry
