On Thu, Feb 13, 2025 at 09:40:09PM +0530, Akhil P Oommen wrote:
> From: Jie Zhang <quic_jiezh@xxxxxxxxxxx>
>
> Add gpu and gmu nodes for qcs8300 chipset.
>
> Signed-off-by: Jie Zhang <quic_jiezh@xxxxxxxxxxx>
> Signed-off-by: Akhil P Oommen <quic_akhilpo@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/qcs8300.dtsi | 93 +++++++++++++++++++++++++++++++++++
> 1 file changed, 93 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qcs8300.dtsi b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> index f1c90db7b0e6..2dc487dcc584 100644
> --- a/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qcs8300.dtsi
> @@ -2660,6 +2660,99 @@ serdes0: phy@8909000 {
> status = "disabled";
> };
>
> + gpu: gpu@3d00000 {
> + compatible = "qcom,adreno-623.0", "qcom,adreno";
> + reg = <0x0 0x03d00000 0x0 0x40000>,
> + <0x0 0x03d9e000 0x0 0x1000>,
> + <0x0 0x03d61000 0x0 0x800>;
> + reg-names = "kgsl_3d0_reg_memory",
> + "cx_mem",
> + "cx_dbgc";
> + interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
> + iommus = <&adreno_smmu 0 0xc00>,
> + <&adreno_smmu 1 0xc00>;
> + operating-points-v2 = <&gpu_opp_table>;
> + qcom,gmu = <&gmu>;
> + interconnects = <&gem_noc MASTER_GFX3D QCOM_ICC_TAG_ALWAYS
> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
> + interconnect-names = "gfx-mem";
> + #cooling-cells = <2>;
> +
> + status = "disabled";
> +
> + gpu_zap_shader: zap-shader {
> + memory-region = <&gpu_microcode_mem>;
> + };
> +
> + gpu_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-877000000 {
> + opp-hz = /bits/ 64 <877000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> + opp-peak-kBps = <12484375>;
> + };
> +
> + opp-780000000 {
> + opp-hz = /bits/ 64 <780000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
> + opp-peak-kBps = <10687500>;
> + };
> +
> + opp-599000000 {
> + opp-hz = /bits/ 64 <599000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
> + opp-peak-kBps = <8171875>;
> + };
> +
> + opp-479000000 {
> + opp-hz = /bits/ 64 <479000000>;
> + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
> + opp-peak-kBps = <5285156>;
> + };
Does it have no speed bins or are they pending on the nvmem patchset?
> + };
> + };
> +
--
With best wishes
Dmitry
