This series covers a step-up towards supporting the DUALPIPE DSC topology, also known as 2:2:2 topology (on active-CTL hardware). It involves 2 layer mixers, 2 DSC compression encoders, and 2 interfaces (on DSI, this is called bonded-DSI) where bandwidth constraints (e.g. 4k panels at 120Hz) require two interfaces to transmit pixel data. Enabling this topology will be hard(er) than downstream as hacking a layout type in DTS won't be describing the hardware, but "dynamically" determining it at runtime may pose some of a challenge that is left to a future series. Such changes will also involve the 1:1:1 topology needed for constrained hardware like the Fairphone 5 on SC7280 with access to only one DSC encoder and thus ruled out of the current 2:2:1 topology. Likewise, the patches and discussions around improving active-CTL configuration to support bonded interfaces (that share a single CTL block) are still in full swing and hence elided from this series, apart from one patch to fix the ACTIVE_DSC register coding to support updates, so that it is not forgotten about. This issue and successful resolution of all the problems is discussed and demonstrated in https://gitlab.freedesktop.org/drm/msm/-/issues/41. Signed-off-by: Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> --- Changes in v2: - Dropped patches that were applied; - dsi_mgr_setup_components() now sets both the usecase and phy_mode prior to calling msm_dsi_host_register(), and for non-bonded too; - Added patch to remove a forced num_intf = 1 when DSC is enabled; - Reworked hdisplay/2 "fix" when calculating "DSC timing" to instead use dsc->slice_count, allowing us to remove msm_dsc_get_slices_per_intf() entirely; - Link to v1: https://lore.kernel.org/r/20240417-drm-msm-initial-dualpipe-dsc-fixes-v1-0-78ae3ee9a697@xxxxxxxxxxxxxx Depends on: - https://lore.kernel.org/linux-arm-msm/20250122-dpu-111-topology-v2-1-505e95964af9@xxxxxxxxxxxxxx/ (only to prevent conflicts with the patch that removes a hardcoded num_intf = 1;). --- Marijn Suijten (3): drm/msm/dsi: Use existing per-interface slice count in DSC timing drm/msm/dsi: Set PHY usescase (and mode) before registering DSI host drm/msm/dpu: Remove arbitrary limit of 1 interface in DSC topology drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 ++++--- drivers/gpu/drm/msm/dsi/dsi_host.c | 8 ++++---- drivers/gpu/drm/msm/dsi/dsi_manager.c | 30 ++++++++++++++++++----------- drivers/gpu/drm/msm/msm_dsc_helper.h | 11 ----------- 4 files changed, 27 insertions(+), 29 deletions(-) --- base-commit: ed58d103e6da15a442ff87567898768dc3a66987 change-id: 20240416-drm-msm-initial-dualpipe-dsc-fixes-3f0715b03bf4 prerequisite-message-id: <20250122-dpu-111-topology-v2-1-505e95964af9@xxxxxxxxxxxxxx> prerequisite-patch-id: 9ed44ae089b173f452a6603e6739b0b3bf2d9274 Best regards, -- Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx>
