> -----Original Message-----
> From: Murthy, Arun R <arun.r.murthy@xxxxxxxxx>
> Sent: Thursday, February 6, 2025 12:13 PM
> To: Kandpal, Suraj <suraj.kandpal@xxxxxxxxx>; intel-xe@xxxxxxxxxxxxxxxxxxxxx;
> intel-gfx@xxxxxxxxxxxxxxxxxxxxx; dri-devel@xxxxxxxxxxxxxxxxxxxxx
> Cc: Shankar, Uma <uma.shankar@xxxxxxxxx>; Kao, Ben <ben.kao@xxxxxxxxx>
> Subject: RE: [PATCH 2/8] drm/dp: Increase eDP display control capability size
>
> > Increase the eDP display control capability size to take into account
> > the general capability register 703 and 704 that have recently been added.
> >
> > Signed-off-by: Suraj Kandpal <suraj.kandpal@xxxxxxxxx>
> > ---
> Reviewed-by: Arun R Murthy <arun.r.murthy@xxxxxxxxx>
>
> Thanks and Regards,
> Arun R Murthy
Hi Maarten,
can I get an ack to merge this from drm-intel-next
Regards,
Suraj Kandpal
> --------------------
> > include/drm/display/drm_dp.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/include/drm/display/drm_dp.h
> > b/include/drm/display/drm_dp.h index 05e16f0144ff..784a32bfbad8
> 100644
> > --- a/include/drm/display/drm_dp.h
> > +++ b/include/drm/display/drm_dp.h
> > @@ -1670,7 +1670,7 @@ enum drm_dp_phy {
> > #define DP_RECEIVER_CAP_SIZE 0xf
> > #define DP_DSC_RECEIVER_CAP_SIZE 0x10 /* DSC Capabilities 0x60
> > through 0x6F */
> > #define EDP_PSR_RECEIVER_CAP_SIZE 2
> > -#define EDP_DISPLAY_CTL_CAP_SIZE 3
> > +#define EDP_DISPLAY_CTL_CAP_SIZE 5
> > #define DP_LTTPR_COMMON_CAP_SIZE 8
> > #define DP_LTTPR_PHY_CAP_SIZE 3
> >
> > --
> > 2.34.1
