On 03/02/2025 18:58, Dmitry Baryshkov wrote:
> On Mon, Feb 03, 2025 at 06:29:21PM +0100, Krzysztof Kozlowski wrote:
>> Add bitfields for PHY_CMN_CLK_CFG0 and PHY_CMN_CLK_CFG1 registers to
>> avoid hard-coding bit masks and shifts and make the code a bit more
>> readable. While touching the lines in dsi_7nm_pll_save_state()
>> resulting cached->pix_clk_div assignment would be too big, so just
>> combine pix_clk_div and bit_clk_div into one cached state to make
>> everything simpler.
>>
>> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
>>
>> ---
>>
>> Changes in v2:
>> 1. New patch
>> ---
>> drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 31 ++++++++++++----------
>> .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 12 +++++++--
>> 2 files changed, 27 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> index 926fd8e3330b2cdfc69d1e0e5d3930abae77b7d8..b61e75a01e1b69f33548ff0adefc5c92980a15d7 100644
>> --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
>> @@ -67,8 +67,7 @@ struct dsi_pll_config {
>>
>> struct pll_7nm_cached_state {
>> unsigned long vco_rate;
>> - u8 bit_clk_div;
>> - u8 pix_clk_div;
>> + u8 clk_div;
>> u8 pll_out_div;
>> u8 pll_mux;
>> };
>> @@ -401,12 +400,12 @@ static void dsi_pll_cmn_clk_cfg1_update(struct dsi_pll_7nm *pll, u32 mask,
>>
>> static void dsi_pll_disable_global_clk(struct dsi_pll_7nm *pll)
>> {
>> - dsi_pll_cmn_clk_cfg1_update(pll, BIT(5), 0);
>> + dsi_pll_cmn_clk_cfg1_update(pll, DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN, 0);
>> }
>>
>> static void dsi_pll_enable_global_clk(struct dsi_pll_7nm *pll)
>> {
>> - u32 cfg_1 = BIT(5) | BIT(4);
>> + u32 cfg_1 = DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN | DSI_7nm_PHY_CMN_CLK_CFG1_CLK_EN_SEL;
>>
>> writel(0x04, pll->phy->base + REG_DSI_7nm_PHY_CMN_CTRL_3);
>> dsi_pll_cmn_clk_cfg1_update(pll, cfg_1, cfg_1);
>> @@ -572,15 +571,17 @@ static void dsi_7nm_pll_save_state(struct msm_dsi_phy *phy)
>> cached->pll_out_div &= 0x3;
>>
>> cmn_clk_cfg0 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG0);
>> - cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
>> - cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
>> + cached->clk_div = cmn_clk_cfg0 & (DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK |
>> + DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK);
>
> Could you rather store these two fields separately by using FIELD_GET?
So make the code again more complicated? OK.
>
>>
>> cmn_clk_cfg1 = readl(phy_base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
>> - cached->pll_mux = cmn_clk_cfg1 & 0x3;
>> + cached->pll_mux = cmn_clk_cfg1 & DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK;
>
> FIELD_GET
>
>>
>> DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
>> - pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div,
>> - cached->pix_clk_div, cached->pll_mux);
>> + pll_7nm->phy->id, cached->pll_out_div,
>> + cached->clk_div & DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK,
>> + cached->clk_div >> DSI_7nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__SHIFT,
>> + cached->pll_mux);
>> }
>>
>> static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
>> @@ -595,9 +596,9 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy *phy)
>> val |= cached->pll_out_div;
>> writel(val, pll_7nm->phy->pll_base + REG_DSI_7nm_PHY_PLL_PLL_OUTDIV_RATE);
>>
>> - dsi_pll_cmn_clk_cfg0_write(pll_7nm,
>> - cached->bit_clk_div | (cached->pix_clk_div << 4));
>> - dsi_pll_cmn_clk_cfg1_update(pll_7nm, 0x3, cached->pll_mux);
>> + dsi_pll_cmn_clk_cfg0_write(pll_7nm, cached->clk_div);
>> + dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK,
>> + cached->pll_mux);
>>
>> ret = dsi_pll_7nm_vco_set_rate(phy->vco_hw,
>> pll_7nm->vco_current_rate,
>> @@ -634,7 +635,8 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy)
>> }
>>
>> /* set PLL src */
>> - dsi_pll_cmn_clk_cfg1_update(pll_7nm, GENMASK(3, 2), data << 2);
>> + dsi_pll_cmn_clk_cfg1_update(pll_7nm, DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL__MASK,
>> + data << DSI_7nm_PHY_CMN_CLK_CFG1_BITCLK_SEL__SHIFT);
>
> use accessor function from the header.
For which part? for last argument? It will be almost pointless, but sure.
>
>>
>> return 0;
>> }
>> @@ -737,7 +739,8 @@ static int pll_7nm_register(struct dsi_pll_7nm *pll_7nm, struct clk_hw **provide
>> u32 data;
>>
>> data = readl(pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
>> - writel(data | 3, pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
>> + writel(data | DSI_7nm_PHY_CMN_CLK_CFG1_DSICLK_SEL__MASK,
>> + pll_7nm->phy->base + REG_DSI_7nm_PHY_CMN_CLK_CFG1);
>>
>> phy_pll_out_dsi_parent = pll_post_out_div;
>> } else {
>> diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
>> index d54b72f924493b4bf0925c287366f7b1e18eb46b..d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367 100644
>> --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
>> +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml
>> @@ -9,8 +9,16 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
>> <reg32 offset="0x00004" name="REVISION_ID1"/>
>> <reg32 offset="0x00008" name="REVISION_ID2"/>
>> <reg32 offset="0x0000c" name="REVISION_ID3"/>
>> - <reg32 offset="0x00010" name="CLK_CFG0"/>
>> - <reg32 offset="0x00014" name="CLK_CFG1"/>
>> + <reg32 offset="0x00010" name="CLK_CFG0">
>> + <bitfield name="DIV_CTRL_3_0" low="0" high="3" type="uint"/>
>> + <bitfield name="DIV_CTRL_7_4" low="4" high="7" type="uint"/>
>
> Are there any sensible names for these two regs? It looks ther are
> not...
These are the sensible names. That's how they are called in datasheet.
Best regards,
Krzysztof
