On Tue, Jan 28, 2025 at 08:47:59PM +0100, Michal Wilczynski wrote: > Add device tree bindings for the TH1520 Video Output (VO) subsystem > clock controller. The VO sub-system manages clock gates for multimedia > components including HDMI, MIPI, and GPU. > > Document the VIDEO_PLL requirements for the VO clock controller, which > receives its input from the AP clock controller. The VIDEO_PLL is a > Silicon Creations Sigma-Delta (integer) PLL typically running at 792 MHz > with maximum FOUTVCO of 2376 MHz. > > This binding complements the existing AP sub-system clock controller > which manages CPU, DPU, GMAC and TEE PLLs. > > Signed-off-by: Michal Wilczynski <m.wilczynski@xxxxxxxxxxx> > --- > .../bindings/clock/thead,th1520-clk-ap.yaml | 17 ++++++++-- > .../dt-bindings/clock/thead,th1520-clk-ap.h | 33 +++++++++++++++++++ > 2 files changed, 47 insertions(+), 3 deletions(-) Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> Best regards, Krzysztof
