Marijn Suijten <marijn.suijten@xxxxxxxxxxxxxx> 于2025年1月20日周一 05:15写道：
>
> On 2025-01-18 00:00:51, Jun Nie wrote:
> > There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd
> > interface to 3rd PP instead of the 2nd PP.
>
> Can you explain why this patch uses the number of LMs, instead of dividing the
> number of PPs divided by the number of physical encoders? This detail is not
> explained at all, or that we're filling hw_lm now for no other reason.
>
> - Marijn
I see LM is 1:1 with PP in catalog header files. So assume their
number are identical
and 1:1 bounded. Using PP number is more formal for sure. Will try to
replace it in
next version.
Jun
>
> > Signed-off-by: Jun Nie <jun.nie@xxxxxxxxxx>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> > Reviewed-by: Jessica Zhang <quic_jesszhan@xxxxxxxxxxx>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 15 +++++++++++++--
> > 1 file changed, 13 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 018a1a49ca7d1..b0cab3ccbb57c 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -1220,7 +1220,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> > struct dpu_hw_blk *hw_pp[MAX_CHANNELS_PER_ENC];
> > struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> > struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> > - int num_ctl, num_pp, num_dsc;
> > + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> > + int num_lm, num_ctl, num_pp, num_dsc, num_pp_per_intf;
> > unsigned int dsc_mask = 0;
> > int i;
> >
> > @@ -1275,11 +1276,21 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc,
> > dpu_enc->cur_master->hw_cdm = hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL;
> > }
> >
> > + num_lm = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > + drm_enc->crtc, DPU_HW_BLK_LM, hw_lm, ARRAY_SIZE(hw_lm));
> > +
> > +
> > + /*
> > + * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not
> > + * mapped to PP 1:1. Let's calculate the stride with pipe/INTF
> > + */
> > + num_pp_per_intf = num_lm / dpu_enc->num_phys_encs;
> > +
> > for (i = 0; i < dpu_enc->num_phys_encs; i++) {
> > struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
> > struct dpu_hw_ctl *ctl0 = to_dpu_hw_ctl(hw_ctl[0]);
> >
> > - phys->hw_pp = dpu_enc->hw_pp[i];
> > + phys->hw_pp = dpu_enc->hw_pp[num_pp_per_intf * i];
> > if (!phys->hw_pp) {
> > DPU_ERROR_ENC(dpu_enc,
> > "no pp block assigned at idx: %d\n", i);
> >
> > --
> > 2.34.1
> >
