Am Dienstag, dem 17.12.2024 um 11:36 +0000 schrieb LECOINTRE Philippe:
> Add optional reset support which is mentioned in vivante,gc.yaml to
> allow the driver to work on SoCs whose reset signal is asserted by default
>
Thanks, applied to etnaviv/next.
Regards,
Lucas
> Signed-off-by: Philippe Lecointre <philippe.lecointre@xxxxxxxxxxxxxxx>
> Acked-by: Simon Lenain <simon.lenain@xxxxxxxxxxxxxxx>
> ---
> v4:
> - Rework to match feedback
> ---
> drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 41 +++++++++++++++++++++++++++
> drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 2 ++
> 2 files changed, 43 insertions(+)
>
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> index 2d4c112ce033..cf0d9049bcf1 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c
> @@ -13,6 +13,7 @@
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> #include <linux/thermal.h>
>
> #include "etnaviv_cmdbuf.h"
> @@ -172,6 +173,29 @@ int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
> return 0;
> }
>
> +static int etnaviv_gpu_reset_deassert(struct etnaviv_gpu *gpu)
> +{
> + int ret;
> +
> + /*
> + * 32 core clock cycles (slowest clock) required before deassertion
> + * 1 microsecond might match all implementations without computation
> + */
> + usleep_range(1, 2);
> +
> + ret = reset_control_deassert(gpu->rst);
> + if (ret)
> + return ret;
> +
> + /*
> + * 128 core clock cycles (slowest clock) required before any activity on AHB
> + * 1 microsecond might match all implementations without computation
> + */
> + usleep_range(1, 2);
> +
> + return 0;
> +}
> +
> static inline bool etnaviv_is_model_rev(struct etnaviv_gpu *gpu, u32 model, u32 revision)
> {
> return gpu->identity.model == model &&
> @@ -799,6 +823,12 @@ int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
> goto pm_put;
> }
>
> + ret = etnaviv_gpu_reset_deassert(gpu);
> + if (ret) {
> + dev_err(gpu->dev, "GPU reset deassert failed\n");
> + goto fail;
> + }
> +
> etnaviv_hw_identify(gpu);
>
> if (gpu->identity.model == 0) {
> @@ -1860,6 +1890,17 @@ static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
> if (IS_ERR(gpu->mmio))
> return PTR_ERR(gpu->mmio);
>
> +
> + /* Get Reset: */
> + gpu->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
> + if (IS_ERR(gpu->rst))
> + return dev_err_probe(dev, PTR_ERR(gpu->rst),
> + "failed to get reset\n");
> +
> + err = reset_control_assert(gpu->rst);
> + if (err)
> + return dev_err_probe(dev, err, "failed to assert reset\n");
> +
> /* Get Interrupt: */
> gpu->irq = platform_get_irq(pdev, 0);
> if (gpu->irq < 0)
> diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
> index 4d8a7d48ade3..5cb46c84e03a 100644
> --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
> +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h
> @@ -93,6 +93,7 @@ struct etnaviv_event {
> struct etnaviv_cmdbuf_suballoc;
> struct regulator;
> struct clk;
> +struct reset_control;
>
> #define ETNA_NR_EVENTS 30
>
> @@ -158,6 +159,7 @@ struct etnaviv_gpu {
> struct clk *clk_reg;
> struct clk *clk_core;
> struct clk *clk_shader;
> + struct reset_control *rst;
>
> unsigned int freq_scale;
> unsigned int fe_waitcycles;
