On 18/12/2024 10.33, Daniel Stone wrote:
+/* MediaTek layouts */
+
+/*
+ * MediaTek Tiled Modifier
+ * This is a tiled layout using tiles of 16x32 pixels in a row-major layout.
+ * For chroma planes this becomes 16x16 tiles.
+ */
+#define DRM_FORMAT_MOD_MTK_16L_32S_TILE fourcc_mod_code(MTK, (1ULL << 0))
I think this probably wants to be something like the tiling mode
defined in AMD/Arm modifiers, i.e. reserve a few bits in the range to
select the tile size, rather than using a single bit here.
Thank you for taking the time, and for your suggestions. Are you
thinking something along the lines of:
/* MediaTek modifiers
* Bits Parameter Notes
* ----- ------------------------
---------------------------------------------
* 3:0 TILE LAYOUT Values are MTK_FMT_MOD_TILE_*
* 7:4 COMPRESSION Values are MTK_FMT_MOD_COMPRESS_*
* 12:8 10 BIT LAYOUT Values are MTK_FMT_MOD_10BIT_LAYOUT_*
*
*/
#define DRM_FORMAT_MOD_MTK(__flags) fourcc_mod_code(MTK, __flags)
/*
* MediaTek Tiled Modifier
* The lowest 4 bits of the modifier is used to specify the tiling
* layout. Only the 16L_32S tiling is used for now, but we define an
* "untiled" version and leave room for future expansion.
*/
#define MTK_FMT_MOD_TILE_MASK 0xf
#define MTK_FMT_MOD_TILE_NONE 0x0
#define MTK_FMT_MOD_TILE_16L32S 0x1
/*
* Bits 4-7 specify compression options
*/
#define MTK_FMT_MOD_COMPRESS_MASK (0xf << 4)
#define MTK_FMT_MOD_COMPRESS_NONE (0x0 << 4)
#define MTK_FMT_MOD_COMPRESS_V1 (0x1 << 4)
/*
* Bits 8-11 specify how the bits of 10 bit formats are
* stored out in memory
*/
#define MTK_FMT_MOD_10BIT_LAYOUT_MASK (0xf << 8)
#define MTK_FMT_MOD_10BIT_LAYOUT_PACKED (0x0 << 8)
#define MTK_FMT_MOD_10BIT_LAYOUT_LSBTILED (0x1 << 8)
#define MTK_FMT_MOD_10BIT_LAYOUT_LSBRASTER (0x2 << 8)
Regards,
Eric
