On Alderlake and later, it's not possible to disable tiling when DPT
is enabled.
So this commit implements Y-Tiling support, to still be able to draw
the panic screen. The Tile-4 support found in the latest Intel GPU
will come later.
Signed-off-by: Jocelyn Falempe <jfalempe@xxxxxxxxxx>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 70 +++++++++++++++++--
.../drm/i915/display/skl_universal_plane.c | 17 +++--
2 files changed, 78 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index bafb1421f3b30..a88f09f6227f5 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -1214,6 +1214,33 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
*/
static struct iosys_map panic_map;
+/* Handle Y-tiling, only if DPT is enabled (otherwise disabling tiling is easier)
+ * All DPT hardware have 128-bytes width tiling, so Y-tile dimension is 32x32
+ * pixels for 32bits pixels.
+ */
+#define YTILE_WIDTH 32
+#define YTILE_HEIGHT 32
+#define YTILE_SIZE (YTILE_WIDTH * YTILE_HEIGHT * 4)
+
+static void intel_ytile_set_pixel(struct drm_scanout_buffer *sb, unsigned int x, unsigned int y,
+ u32 color)
+{
+ u32 offset;
+ unsigned int swizzle;
+ unsigned int width_in_blocks = DIV_ROUND_UP(sb->width, 32);
+
+ /* Block offset */
+ offset = ((y / YTILE_HEIGHT) * width_in_blocks + (x / YTILE_WIDTH)) * YTILE_SIZE;
+
+ x = x % YTILE_WIDTH;
+ y = y % YTILE_HEIGHT;
+
+ /* bit order inside a block is x4 x3 x2 y4 y3 y2 y1 y0 x1 x0 */
+ swizzle = (x & 3) | ((y & 0x1f) << 2) | ((x & 0x1c) << 5);
+ offset += swizzle * 4;
+ iosys_map_wr(&sb->map[0], offset, u32, color);
+}
+
static void intel_panic_flush(struct drm_plane *plane)
{
struct intel_plane_state *plane_state = to_intel_plane_state(plane->state);
@@ -1232,6 +1259,34 @@ static void intel_panic_flush(struct drm_plane *plane)
iplane->disable_tiling(iplane);
}
+static void (*intel_get_tiling_func(u64 fb_modifier))(struct drm_scanout_buffer *sb, unsigned int x,
+ unsigned int y, u32 color)
+{
+ switch (fb_modifier) {
+ case I915_FORMAT_MOD_Y_TILED:
+ case I915_FORMAT_MOD_Y_TILED_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS:
+ case I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS:
+ return intel_ytile_set_pixel;
+ case I915_FORMAT_MOD_X_TILED:
+ case I915_FORMAT_MOD_4_TILED:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+ case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+ case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS:
+ case I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC:
+ case I915_FORMAT_MOD_4_TILED_MTL_MC_CCS:
+ case I915_FORMAT_MOD_4_TILED_BMG_CCS:
+ case I915_FORMAT_MOD_4_TILED_LNL_CCS:
+ case I915_FORMAT_MOD_Yf_TILED:
+ case I915_FORMAT_MOD_Yf_TILED_CCS:
+ default:
+ /* Not supported yet */
+ return NULL;
+ }
+}
+
static int intel_get_scanout_buffer(struct drm_plane *plane,
struct drm_scanout_buffer *sb)
{
@@ -1254,9 +1309,13 @@ static int intel_get_scanout_buffer(struct drm_plane *plane,
ptr = intel_fbdev_get_vaddr(dev_priv->display.fbdev.fbdev);
} else {
/* Can't disable tiling if DPT is in use */
- if (intel_fb_uses_dpt(fb))
- return -EOPNOTSUPP;
-
+ if (intel_fb_uses_dpt(fb)) {
+ if (fb->format->cpp[0] != 4)
+ return -EOPNOTSUPP;
+ sb->set_pixel = intel_get_tiling_func(fb->modifier);
+ if (!sb->set_pixel)
+ return -EOPNOTSUPP;
+ }
ptr = intel_bo_panic_map(obj);
}
@@ -1271,7 +1330,10 @@ static int intel_get_scanout_buffer(struct drm_plane *plane,
sb->map[0] = panic_map;
sb->width = fb->width;
sb->height = fb->height;
- sb->format = fb->format;
+ /* Use the generic linear format, because tiling, RC, CCS, CC
+ * will be disabled in disable_tiling()
+ */
+ sb->format = drm_format_info(fb->format->format);
sb->pitch[0] = fb->pitches[0];
return 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index e2a54547a29d5..71e79b022c9ef 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -2577,17 +2577,24 @@ static u8 skl_get_plane_caps(struct drm_i915_private *i915,
static void skl_disable_tiling(struct intel_plane *plane)
{
- u32 plane_ctl;
struct intel_plane_state *state = to_intel_plane_state(plane->base.state);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- u32 stride = state->view.color_plane[0].scanout_stride / 64;
+ const struct drm_framebuffer *fb = state->hw.fb;
+ u32 plane_ctl;
plane_ctl = intel_de_read(dev_priv, PLANE_CTL(plane->pipe, plane->id));
- plane_ctl &= ~PLANE_CTL_TILED_MASK;
- intel_de_write_fw(dev_priv, PLANE_STRIDE(plane->pipe, plane->id),
- PLANE_STRIDE_(stride));
+ if (intel_fb_uses_dpt(fb)) {
+ /* if DPT is enabled, keep tiling, but disable compression */
+ plane_ctl &= ~PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
+ } else {
+ /* if DPT is not supported, disable tiling, and update stride */
+ u32 stride = state->view.color_plane[0].scanout_stride / 64;
+ plane_ctl &= ~PLANE_CTL_TILED_MASK;
+ intel_de_write_fw(dev_priv, PLANE_STRIDE(plane->pipe, plane->id),
+ PLANE_STRIDE_(stride));
+ }
intel_de_write_fw(dev_priv, PLANE_CTL(plane->pipe, plane->id), plane_ctl);
intel_de_write_fw(dev_priv, PLANE_SURF(plane->pipe, plane->id),
--
2.47.1
