Re: [PATCH v2] drm: bridge: fsl-ldb: fixup mode on freq mismatch

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On 12/3/24 8:09 PM, Nikolaus Voss wrote:
LDB clock has to be a fixed multiple of the pixel clock.
As LDB and pixel clock are derived from different clock sources

Can you please share the content of /sys/kernel/debug/clk/clk_summary ?

LDB and matching LCDIF should use the same PLL on MX8MP , else you might really run into odd issues.



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