On 27/11/2024 17:00, Akhil P Oommen wrote:
On 11/25/2024 1:46 PM, Neil Armstrong wrote:
On 23/11/2024 20:43, Akhil P Oommen wrote:
On Tue, Nov 19, 2024 at 06:56:39PM +0100, Neil Armstrong wrote:
The Adreno GMU Management Unit (GNU) can also scale the DDR Bandwidth
along the Frequency and Power Domain level, but by default we leave the
OPP core vote for the interconnect ddr path.
While scaling via the interconnect path was sufficient, newer GPUs
like the A750 requires specific vote paremeters and bandwidth to
achieve full functionality.
While the feature will require some data in a6xx_info, it's safer
to only enable tested platforms with this flag first.
Add a new feature enabling DDR Bandwidth vote via GMU.
Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
---
drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/
drm/msm/adreno/adreno_gpu.h
index
4702d4cfca3b58fb3cbb25cb6805f1c19be2ebcb..394b96eb6c83354ae008b15b562bedb96cd391dd 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h
@@ -58,6 +58,7 @@ enum adreno_family {
#define ADRENO_FEAT_HAS_HW_APRIV BIT(0)
#define ADRENO_FEAT_HAS_CACHED_COHERENT BIT(1)
#define ADRENO_FEAT_PREEMPTION BIT(2)
+#define ADRENO_FEAT_GMU_BW_VOTE BIT(3)
Do we really need a feature flag for this? We have to carry this for
every
GPU going forward. IB voting is supported on all GMUs from A6xx GEN2 and
newer. So we can just check that along with whether the bw table is
dynamically generated or not.
It depends on the bw table _and_ the a6xx_info.gmu table, I don't want to
check both in all parts on the driver.
Thats fine then.
Finally I converted the a6xx_info to a pointer, and it's fine checking
this pointer instead of the quirk, since anyway we already check num_bws.
Neil
-Akhil.
Neil
-Akhil
/* Helper for formating the chip_id in the way that userspace
tools like
* crashdec expect.
--
2.34.1
