On Mon, Nov 25, 2024 at 06:03:52PM -0800, Abhinav Kumar wrote: > > > On 11/22/2024 9:44 PM, Dmitry Baryshkov wrote: > > Rather than hand-coding UBWC_STATIC value calculation, define > > corresponding bitfields and use them to setup the register value. > > > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx> > > --- > > drivers/gpu/drm/msm/msm_mdss.c | 38 +++++++++++++++----------- > > drivers/gpu/drm/msm/msm_mdss.h | 3 +- > > drivers/gpu/drm/msm/registers/display/mdss.xml | 11 +++++++- > > 3 files changed, 34 insertions(+), 18 deletions(-) > > > > <snip> > > > diff --git a/drivers/gpu/drm/msm/registers/display/mdss.xml b/drivers/gpu/drm/msm/registers/display/mdss.xml > > index ac85caf1575c7908bcf68f0249da38dccf4f07b6..b6f93984928522a35a782cbad9de006eac225725 100644 > > --- a/drivers/gpu/drm/msm/registers/display/mdss.xml > > +++ b/drivers/gpu/drm/msm/registers/display/mdss.xml > > @@ -21,7 +21,16 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> > > <reg32 offset="0x00058" name="UBWC_DEC_HW_VERSION"/> > > - <reg32 offset="0x00144" name="UBWC_STATIC"/> > > + <reg32 offset="0x00144" name="UBWC_STATIC"> > > + <bitfield name="UBWC_SWIZZLE" low="0" high="2"/> > > + <bitfield name="UBWC_BANK_SPREAD" pos="3"/> > > + <!-- high=5 for UBWC < 4.0 --> > > + <bitfield name="HIGHEST_BANK_BIT" low="4" high="6"/> > > + <bitfield name="UBWC_MIN_ACC_LEN" pos="8"/> > > MIN_ACC_LEN OR MALSIZE has 2 bits , bits 8 and 9. > > But bit 9 is unused today. Hence we were using it as a 1 or 0 today. > > Its unused on all the chipsets I checked. Do you want to continue using the > same way or correct this? Let's correct it. I will send next iteration. -- With best wishes Dmitry
