adam > > > > > >> [...] > > >> > > >>>> Can something like (*) above be implemented instead, so both Shared > > >> and > > >>>> separate PLLs would be supported ? That should solve both of our use > > >>>> cases, right ? > > >>> > > >>> I don't see any clear way to implement something like(*). > > >>> > > >>> Take the 3 i.MX8MP LCDIFs as one graphic card driven by one imx-lcdif > > >>> DRM instance? Would it be too intrusive? > > >> > > >> Yes, and I think unnecessary, one can simply traverse and parse the DT > > >> to determine the clock assignment? > > > > > > Yes, people can traverse and parse DT, but it's nasty. > > > > > > In addition, one may argue that now that CLK_SET_RATE_PARENT flag > > > is set for the pixel clocks, all potential video modes read from EDID > > > should be supported when only either LVDS display pipeline or MIPI DSI > > > display pipeline is active in the shared PLL case. This requires one > > > single DRM instance to detect single or dual active display pipelines > > > dynamically, hence this single DRM instance becomes necessary. > > > > Would single virtual clock which do the frequency negotiation between > > multiple DRM consumers work too ? > > Not sure if it would work or not, but I'm sure that one single DRM instance > means atomic check/commit for the display pipelines as a whole, hence > awareness of active display pipeline number in an atomic way. > > > > > I do not have much to add to the points below. > > Regards, > Liu Ying
