On Sat, 16 Nov 2024 20:22:32 +0200, Cristian Ciocaltea wrote: > On RK3588, HDMI PHY PLL can be used as an alternative and more accurate > pixel clock source for VOP2 video ports 0, 1 and 2. > > Document the optional PLL clock properties corresponding to the two HDMI > PHYs available on the SoC. > > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@xxxxxxxxxxxxx> > --- > Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > Acked-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
