Current tc358775 bridge driver implementation assumes that DSI clock
is used as a source for LVDS pixel clock. Moreover, clock divider
PCLKDIV has a hard-coded value. This means that driver expects DSI
clock to always match a panel pixel clock. With such assumption, LVDS
pixel clock is configured to be (DSI pixel clock / 3) for single link.
This is true for DSI non-burst video modes. In burst mode, DSI host
is allowed to set transmission rate higher than pixel clock to allow
shorter data bursts. When the transmission rate is higher than expected
by the bridge, LVDS output timings are still configured for the lower
frequency, but the output is clocked with the higher one. In most cases,
bad LVDS timings cause incorrect panel operation.
Remove support for burst mode, so the non-burst mode is used by DSI
host by default. Burst mode is supported by the bridge itself,
but requires proper implementation in the driver to operate correctly
in all scenarios.
Fixes: a4ed72e85c46 ("drm/bridge: tc358775: Add burst and low-power modes")
Signed-off-by: Daniel Semkowicz <dse@xxxxxxxxxxxxx>
---
drivers/gpu/drm/bridge/tc358775.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358775.c b/drivers/gpu/drm/bridge/tc358775.c
index 0b4efaca6d682..7496681c7b883 100644
--- a/drivers/gpu/drm/bridge/tc358775.c
+++ b/drivers/gpu/drm/bridge/tc358775.c
@@ -632,8 +632,7 @@ static int tc_attach_host(struct tc_data *tc)
dsi->lanes = tc->num_dsi_lanes;
dsi->format = MIPI_DSI_FMT_RGB888;
- dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
- MIPI_DSI_MODE_LPM;
+ dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
/*
* The hs_rate and lp_rate are data rate values. The HS mode is
--
2.47.0
