Hi Detlev,
Am Freitag, 8. November 2024, 19:50:39 CET schrieb Detlev Casanova:
> At the end of initialization, each VP clock needs to be reset before
> they can be used.
>
> Failing to do so can put the VOP in an undefined state where the
> generated HDMI signal is either lost or not matching the selected mode.
>
> This issue can be reproduced by switching modes multiple times.
> Depending on the setup, after about 10 mode switches, the signal will be
> lost and the value in register 0x890 (VSYNCWIDTH + VFRONT) will take the value
> `0x0000018c`.
> That makes VSYNCWIDTH=0, which is wrong.
>
> Adding the clock resets after the VOP configuration fixes the issue.
>
> Signed-off-by: Detlev Casanova <detlev.casanova@xxxxxxxxxxxxx>
patch subject should be "drm/rockchip: vop2: ...." please
> static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
> struct drm_atomic_state *state)
> {
> @@ -2057,6 +2079,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
>
> vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
>
> + vop2_clk_reset(vp);
> +
> drm_crtc_vblank_on(crtc);
>
> vop2_unlock(vop2);
this conflicts with the merge gamma lut support, can you please rebase on
top of drm-misc-next? Or alternatively just tell me if it should be
vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
+ vop2_clk_reset(vp);
+
vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);
drm_crtc_vblank_on(crtc);
----- or ----
vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
vop2_crtc_atomic_try_set_gamma(vop2, vp, crtc, crtc_state);
+ vop2_clk_reset(vp);
+
drm_crtc_vblank_on(crtc);
Thanks a lot
Heiko
