On Fri, Nov 08, 2024 at 07:36:16PM +0530, Parthiban wrote: > To add, 0x20 will be DE0 <--> LCD0 and DE1 <--> TV0. Below note (copied from > R40) states the priority of the DE selection, which fails to work? Not sure, > may be disabling CORE1_SCLK_GATE and CORE1_HCLK_GATE in de2-clk helps. > > With A133 following the same as T113 with single mixer without TV, still > sets 0x20 in vendor kernel. > > copied from R40: > Note: The priority of DE0 is higher than DE1. > If TCON_LCD0 selects DE0 and DE1 as source at the same time, then > DE0 will be used for the source of TCON_LCD0. Hi there, Yes that was a pretty bad typo, I meant to say DE1 to TV0 The prioritization seems broken in the T113 at least, it's racy from what I see in testing. I should note this in the patch too. I looked at the datasheets and kernel code briefly: I can't seem to figure out what SCLK/HCLK gating does and I don't think the kernel touches these registers which are gated by default. > Thanks, > Parthiban John Watts
