Verisilicon hardware video decoders can produce tiled (8x4 or 4x4) and compressed video framebuffers. It considerably reduces memory bandwidth while writing and reading frames in memory. The underlying storage in NV12 (for 8-bit) or NV15 (for 10-bit). Display controllers, like imx DCSS, could use these modifier definition as input for overlay planes. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@xxxxxxxxxxxxx> --- The original code comes from: https://github.com/nxp-imx/linux-imx/commit/ab01b7fe82d5a11dfb533cfbd08c4dfa140815de I have port it and modify DRM_FORMAT_MOD_VENDOR_VSI value. include/uapi/drm/drm_fourcc.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h index 78abd819fd62..31d09a98d0d7 100644 --- a/include/uapi/drm/drm_fourcc.h +++ b/include/uapi/drm/drm_fourcc.h @@ -421,6 +421,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a +#define DRM_FORMAT_MOD_VENDOR_VSI 0x0b /* add more to the end as needed */ @@ -1607,6 +1608,32 @@ drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier) #define AMD_FMT_MOD_CLEAR(field) \ (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) +/* Verisilicon framebuffer modifiers */ + +/* + * Verisilicon 8x4 tiling layout + * + * This is G1 VPU tiled layout using tiles of 8x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VSI_G1_TILED fourcc_mod_code(VSI, 1) + +/* + * Verisilicon 4x4 tiling layout + * + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major + * layout. + */ +#define DRM_FORMAT_MOD_VSI_G2_TILED fourcc_mod_code(VSI, 2) + +/* + * Verisilicon 4x4 tiling with compression layout + * + * This is G2 VPU tiled layout using tiles of 4x4 pixels in a row-major + * layout with compression. + */ +#define DRM_FORMAT_MOD_VSI_G2_TILED_COMPRESSED fourcc_mod_code(VSI, 3) + #if defined(__cplusplus) } #endif -- 2.43.0
