The LVDS panel "multi-inno,mi1010ait-1cp" used on this platform has
a typical pixel clock rate of 70MHz. Set "media_disp2_pix" clock rate
to that rate, instead of the original 68.9MHz. The LVDS serial clock
is controlled by "media_ldb" clock. It should run at 490MHz(7-fold the
pixel clock rate due to single LVDS link). Set "video_pll1" clock rate
and "media_ldb" to 490MHz to achieve that.
This should be able to suppress this LDB driver warning:
[ 17.206644] fsl-ldb 32ec0000.blk-ctrl:bridge@5c: Configured LDB clock (70000000 Hz) does not match requested LVDS clock: 490000000 Hz
This also makes the display mode used by the panel pass mode validation
against pixel clock rate and "media_ldb" clock rate in a certain display
driver.
Signed-off-by: Liu Ying <victor.liu@xxxxxxx>
---
v4:
* No change.
v3:
* New patch.
.../dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
index 30962922b361..2c75da5f064f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts
@@ -52,7 +52,7 @@ &lcdif2 {
&lvds_bridge {
/* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */
- assigned-clock-rates = <482300000>;
+ assigned-clock-rates = <490000000>;
status = "okay";
ports {
@@ -70,10 +70,10 @@ &media_blk_ctrl {
*/
assigned-clock-rates = <500000000>, <200000000>, <0>,
/* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */
- <68900000>,
+ <70000000>,
<500000000>,
- /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */
- <964600000>;
+ /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB */
+ <490000000>;
};
&pwm4 {
--
2.34.1
