The Pixel PLL is not very capable and may come up with wildly inaccurate
clock. Since DPI panels are often tolerant to slightly higher pixel clock
without being operated outside of specification, calculate two Pixel PLL
settings for DPI output, one for desired output pixel clock and one for
output pixel clock with 1% increase, and then pick the result which is
closer to the desired pixel clock and use it as the Pixel PLL settings.
For the Chefree CH101 panel with 13 MHz Xtal input clock, the frequency
without this patch is 65 MHz which is out of the panel specification of
68.9..73.4 MHz, while with this patch it is 71.5 MHz which is well within
the specification and far more accurate.
Keep the change isolated to DPI output.
Signed-off-by: Marek Vasut <marex@xxxxxxx>
---
Cc: Andrzej Hajda <andrzej.hajda@xxxxxxxxx>
Cc: David Airlie <airlied@xxxxxxxxx>
Cc: Jernej Skrabec <jernej.skrabec@xxxxxxxxx>
Cc: Jonas Karlman <jonas@xxxxxxxxx>
Cc: Laurent Pinchart <Laurent.pinchart@xxxxxxxxxxxxxxxx>
Cc: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
Cc: Maxime Ripard <mripard@xxxxxxxxxx>
Cc: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
Cc: Robert Foss <rfoss@xxxxxxxxxx>
Cc: Simona Vetter <simona@xxxxxxxx>
Cc: Thomas Zimmermann <tzimmermann@xxxxxxx>
Cc: dri-devel@xxxxxxxxxxxxxxxxxxxxx
---
V2: Isolate the change to DPI only, split tc_bridge_mode_set()
---
drivers/gpu/drm/bridge/tc358767.c | 47 ++++++++++++++++++++++++++-----
1 file changed, 40 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c
index 7968183510e63..84c1429321c43 100644
--- a/drivers/gpu/drm/bridge/tc358767.c
+++ b/drivers/gpu/drm/bridge/tc358767.c
@@ -1682,15 +1682,39 @@ static int tc_dpi_atomic_check(struct drm_bridge *bridge,
struct drm_connector_state *conn_state)
{
struct tc_data *tc = bridge_to_tc(bridge);
- int adjusted_clock = 0;
+ int adjusted_clock_0p = 0;
+ int adjusted_clock_1p = 0;
+ int adjusted_clock;
int ret;
+ /*
+ * Calculate adjusted clock pixel and find out what the PLL can
+ * produce. The PLL is limited, so the clock might be inaccurate.
+ */
ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
crtc_state->mode.clock * 1000,
- &adjusted_clock, NULL);
+ &adjusted_clock_0p, NULL);
if (ret)
return ret;
+ /*
+ * Calculate adjusted pixel clock with 1% faster requested pixel
+ * clock and find out what the PLL can produce. This may in fact
+ * be closer to the expected pixel clock of the output.
+ */
+ ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk),
+ crtc_state->mode.clock * 1010,
+ &adjusted_clock_1p, NULL);
+ if (ret)
+ return ret;
+
+ /* Pick the more accurate of the two calculated results. */
+ if (crtc_state->mode.clock * 1010 - adjusted_clock_1p <
+ crtc_state->mode.clock * 1000 - adjusted_clock_0p)
+ adjusted_clock = adjusted_clock_1p;
+ else
+ adjusted_clock = adjusted_clock_0p;
+
crtc_state->adjusted_mode.clock = adjusted_clock / 1000;
/* DSI->DPI interface clock limitation: upto 100 MHz */
@@ -1758,9 +1782,18 @@ tc_edp_mode_valid(struct drm_bridge *bridge,
return MODE_OK;
}
-static void tc_bridge_mode_set(struct drm_bridge *bridge,
- const struct drm_display_mode *mode,
- const struct drm_display_mode *adj)
+static void tc_dpi_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adj)
+{
+ struct tc_data *tc = bridge_to_tc(bridge);
+
+ drm_mode_copy(&tc->mode, adj);
+}
+
+static void tc_edp_bridge_mode_set(struct drm_bridge *bridge,
+ const struct drm_display_mode *mode,
+ const struct drm_display_mode *adj)
{
struct tc_data *tc = bridge_to_tc(bridge);
@@ -1977,7 +2010,7 @@ tc_edp_atomic_get_output_bus_fmts(struct drm_bridge *bridge,
static const struct drm_bridge_funcs tc_dpi_bridge_funcs = {
.attach = tc_dpi_bridge_attach,
.mode_valid = tc_dpi_mode_valid,
- .mode_set = tc_bridge_mode_set,
+ .mode_set = tc_dpi_bridge_mode_set,
.atomic_check = tc_dpi_atomic_check,
.atomic_enable = tc_dpi_bridge_atomic_enable,
.atomic_disable = tc_dpi_bridge_atomic_disable,
@@ -1991,7 +2024,7 @@ static const struct drm_bridge_funcs tc_edp_bridge_funcs = {
.attach = tc_edp_bridge_attach,
.detach = tc_edp_bridge_detach,
.mode_valid = tc_edp_mode_valid,
- .mode_set = tc_bridge_mode_set,
+ .mode_set = tc_edp_bridge_mode_set,
.atomic_check = tc_edp_atomic_check,
.atomic_enable = tc_edp_bridge_atomic_enable,
.atomic_disable = tc_edp_bridge_atomic_disable,
--
2.45.2
