On Fri, 25 Oct 2024 10:24:32 +0100 Liviu Dudau <liviu.dudau@xxxxxxx> wrote: > On Thu, Oct 24, 2024 at 05:49:44PM +0200, Boris Brezillon wrote: > > +Robin for the MMU details > > > > On Thu, 24 Oct 2024 15:54:30 +0100 > > Akash Goel <akash.goel@xxxxxxx> wrote: > > > > > Mali GPU Arch spec forbids the GPU PTEs to indicate Inner or Outer > > > shareability when no_coherency protocol is selected. Doing so results in > > > unexpected or undesired snooping of the CPU caches on some platforms, > > > such as Juno FPGA, causing functional issues. For example the boot of > > > MCU firmware fails as GPU ends up reading stale data for the FW memory > > > pages from the CPU's cache. The FW memory pages are initialized with > > > uncached mapping when the device is not reported to be dma-coherent. > > > The shareability bits are set to inner-shareable when IOMMU_CACHE flag > > > is passed to map_pages() callback and IOMMU_CACHE flag is passed by > > > Panthor driver when memory needs to be mapped as cached on the GPU side. > > > > > > IOMMU_CACHE seems to imply cache coherent and is probably not fit for > > > purpose for the memory that is mapped as cached on GPU side but doesn't > > > need to remain coherent with the CPU. > > > > Yeah, IIRC I've been abusing the _CACHE flag to mean GPU-cached, not > > cache-coherent. I think it be good to sit down with Rob and add the > > necessary IOMMU_ flags so we can express all the shareability and > > cacheability variants we have with the "Mali" MMU. For instance, I > > think the shareability between MCU/GPU can be expressed properly at the > > moment, and we unconditionally map things uncached because of that. > > Boris, did you mean to say "shareability between MCU/GPU *can't* be expressed > properly" ? Currently the sentence reads a bit strange, as if there was a > negation somewhere. Yes, sorry, I meant "can't".
