On Tue, Oct 22, 2024 at 04:10:51PM +0800, Liu Ying wrote:
> Hi Maxime,
>
> On 10/22/2024, Maxime Ripard wrote:
> > On Tue, Oct 22, 2024 at 03:36:47PM +0800, Liu Ying wrote:
> >> Hi Maxime,
> >>
> >> On 10/21/2024, Maxime Ripard wrote:
> >>> On Mon, Oct 21, 2024 at 02:44:43PM +0800, Liu Ying wrote:
> >>>> +static int it6263_bridge_atomic_check(struct drm_bridge *bridge,
> >>>> + struct drm_bridge_state *bridge_state,
> >>>> + struct drm_crtc_state *crtc_state,
> >>>> + struct drm_connector_state *conn_state)
> >>>> +{
> >>>> + struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> >>>> + int ret;
> >>>> +
> >>>> + ret = drm_atomic_helper_connector_hdmi_check(conn_state->connector,
> >>>> + conn_state->state);
> >>>> + if (ret)
> >>>> + return ret;
> >>>> +
> >>>> + return mode->clock > MAX_PIXEL_CLOCK_KHZ ? -EINVAL : 0;
> >>>
> >>> drm_atomic_helper_connector_hdmi_check will already make that check, so
> >>> it's redundant.
> >>
> >> MAX_PIXEL_CLOCK_KHZ is 150MHz. With 150MHz pixel clock rate, we'll get
> >> 150MHz HDMI character rate for 8bpc and 187.5MHz HDMI character rate
> >> for 10bpc, both are lower than MAX_HDMI_TMDS_CHAR_RATE_HZ = 225MHz.
> >
> > I guess? I have no idea how that's relevant though. Where are those
> > constraints coming from, and why aren't you checking for them in
> > tmds_char_rate_valid?
>
> All constraints come from IT6263 data sheet. They are also mentioned
> in IT6263 product link(commit message contains the link).
>
> https://www.ite.com.tw/en/product/cate1/IT6263
>
> "
> LVDS RX
> Support input clock rate up to 150 MHz
>
> HDMI TX
> Support link speeds of up to 2.25 Gbps (link clock rate of 225 MHz)
> "
>
> If no objection, I'll check mode clock rate against
> MAX_PIXEL_CLOCK_KHZ in tmds_char_rate_valid.
If you don't support bpc other than 8, and no other format than RGB,
then it's a good enough approximation.
It should be documented though
Maxime
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