Hi Aradhya,
Thanks for the patch.
On 20/10/24 01:24, Aradhya Bhatia wrote:
> From: Aradhya Bhatia <a-bhatia1@xxxxxx>
[...]
> + /*
> + * Now that the DSI Link and DSI Phy are initialized,
> + * wait for the CLK and Data Lanes to be ready.
> + */
> + tmp = CLK_LANE_RDY;
> + for (int i = 0; i < nlanes; i++)
> + tmp |= DATA_LANE_RDY(i);
> +
> + if (readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
> + status & tmp, 100, 500000))
The above would mark the condition as true even if one data lane gets ready. I
think we need to poll until all data lanes are marked as ready. Also good to
give a warning in case we time out.
IMHO below should fix this:
WARN_ON_ONCE(readl_poll_timeout(dsi->regs + MCTL_MAIN_STS, status,
(tmp == (status & tmp)), 100, 0));
Regards
Devarsh
