Hi, Am Freitag, 18. Oktober 2024, 08:48:12 CEST schrieb Liu Ying: > Set DW HDMI platform data's output_port to 1 in imx8mp_dw_hdmi_probe() > so that dw_hdmi_probe() called by imx8mp_dw_hdmi_probe() can tell the > DW HDMI bridge core driver about the output port we are using, hence > the next bridge can be found in dw_hdmi_parse_dt() according to the port > index, and furthermore the next bridge can be attached to bridge chain in > dw_hdmi_bridge_attach() when the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag is > set. The output_port value aligns to the value used by devicetree. > This is a preparation for making the i.MX8MP LCDIF driver use > drm_bridge_connector which requires the DRM_BRIDGE_ATTACH_NO_CONNECTOR > flag. > > Signed-off-by: Liu Ying <victor.liu@xxxxxxx> Reviewed-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx> > --- > drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c > index 8fcc6d18f4ab..54a53f96929a 100644 > --- a/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c > +++ b/drivers/gpu/drm/bridge/imx/imx8mp-hdmi-tx.c > @@ -96,6 +96,7 @@ static int imx8mp_dw_hdmi_probe(struct platform_device *pdev) > return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), > "Unable to get pixel clock\n"); > > + plat_data->output_port = 1; > plat_data->mode_valid = imx8mp_hdmi_mode_valid; > plat_data->phy_ops = &imx8mp_hdmi_phy_ops; > plat_data->phy_name = "SAMSUNG HDMI TX PHY"; > -- TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany Amtsgericht München, HRB 105018 Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider http://www.tq-group.com/
