On Tue, Oct 15, 2024 at 03:33:00PM GMT, Krzysztof Kozlowski wrote:
> On 15/10/2024 14:07, Jyothi Kumar Seerapu wrote:
> > When high performance with multiple i2c messages in a single transfer
> > is required, employ Block Event Interrupt (BEI) to trigger interrupts
> > after specific messages transfer and the last message transfer,
> > thereby reducing interrupts.
> > For each i2c message transfer, a series of Transfer Request Elements(TREs)
> > must be programmed, including config tre for frequency configuration,
> > go tre for holding i2c address and dma tre for holding dma buffer address,
> > length as per the hardware programming guide. For transfer using BEI,
> > multiple I2C messages may necessitate the preparation of config, go,
> > and tx DMA TREs. However, a channel TRE size of 64 is often insufficient,
> > potentially leading to failures due to inadequate memory space.
> >
> > Adjust the channel TRE size through the device tree.
> > The default size is 64, but clients can modify this value based on
> > their heigher channel TRE size requirements.
> >
> > Signed-off-by: Jyothi Kumar Seerapu <quic_jseerapu@xxxxxxxxxxx>
> > ---
> > arch/arm64/boot/dts/qcom/sc7280.dtsi | 132 +++++++++++++--------------
> > 1 file changed, 66 insertions(+), 66 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index 3d8410683402..c7c0e15ff9d3 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -1064,7 +1064,7 @@
> > };
> >
> > gpi_dma0: dma-controller@900000 {
> > - #dma-cells = <3>;
> > + #dma-cells = <4>;
> > compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma";
> > reg = <0 0x00900000 0 0x60000>;
> > interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
> > @@ -1114,8 +1114,8 @@
> > "qup-memory";
> > power-domains = <&rpmhpd SC7280_CX>;
> > required-opps = <&rpmhpd_opp_low_svs>;
> > - dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
> > - <&gpi_dma0 1 0 QCOM_GPI_I2C>;
> > + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C 64>,
> > + <&gpi_dma0 1 0 QCOM_GPI_I2C 64>;
>
> So everywhere is 64, thus this is fixed. Deduce it from the compatible
>
If I understand correctly, it's a software tunable property, used to
balance how many TRE elements that should be preallocated.
If so, it would not be a property of the hardware/compatible, but rather
a result of profiling and a balance between memory "waste" and
performance.
Regards,
Bjorn
> Best regards,
> Krzysztof
>
