Hi Marek,
On Sat, 2024-07-06 at 02:16 +0200, Marek Vasut wrote:
> On 6/24/24 11:19 AM, Alexander Stein wrote:
> > Am Freitag, 31. Mai 2024, 22:27:21 CEST schrieb Marek Vasut:
> > > In case an upstream bridge modified the required clock frequency
> > > in its .atomic_check callback by setting adjusted_mode.clock ,
> > > make sure that clock frequency is generated by the LCDIFv3 block.
> > >
> > > This is useful e.g. when LCDIFv3 feeds DSIM which feeds TC358767
> > > with (e)DP output, where the TC358767 expects precise timing on
> > > its input side, the precise timing must be generated by the
> > > LCDIF.
> > >
> > > Signed-off-by: Marek Vasut <marex@xxxxxxx>
> >
> > With the other rc358767 patches in place, this does the trick.
> > Reviewed-by: Alexander Stein <alexander.stein@xxxxxxxxxxxxxxx>
>
> I'll pick this up next week if there is no objection.
Unfortunately, this has caused a regression that is present in v6.12-
rc1 on the i.MX8MP PHYTEC Pollux using the
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts. The
display is the edt,etml1010g3dra panel, as per the upstream dts. We
bisected to this commit, and reverting this change fixed the screen.
We then tried to retest this on top of v6.12-rc2, and found we also had
to revert commit ff06ea04e4cf3ba2f025024776e83bfbdfa05155 ("clk: imx:
clk-imx8mp: Allow media_disp pixel clock reconfigure parent rate")
alongside this. Reverting these two commits makes the display work
again at -rc2.
Do you have any suggestions on anything we might be missing on our end?
Please let me know if there's anything you'd like me to test as I'm not
sure what the underlying fault was here.
Best wishes,
Isaac
